Full color independent video LED system based on ARM and FPGA

At present, there are two main types of display transmission methods according to data: one is a real-time video screen that displays the same content as a computer; the other is an independent video source that sends display content to the display through communication means such as USB or Ethernet. The display screen can update the display content at any time if the wireless communication method is adopted, and the flexibility is high. In addition, replacing the computer with a set of embedded systems to provide a video source can reduce costs, be highly feasible and flexible, and be easy to construct. Therefore, the demand for independent video source LED display systems is growing.

The system adopts ARM+FPGA architecture, which makes full use of ARM's powerful processing capability and rich interface to realize real network remote operation. Therefore, it can not only be used as a general LED display controller, but also can form large display nodes. Outdoor advertising media network. The FPGA is a very flexible programmable logic device that can be programmed like software to enable flexible and convenient change and development in real time, improving system efficiency.

1 independent video LED system


The main performance indicators of LED display screens include field scanning frequency, resolution, gray level and brightness. The resolution refers to the number of LED tubes that the controller can control. The gray level is the resolution of the color, and the high brightness requires the display time of each gray level to be long. Obviously, these three indicators will greatly reduce the frequency of field scans, so it is necessary to make appropriate trade-offs for these indicators in different situations. Usually the gray level, brightness and field scan frequency are determined by a single controller, and the resolution can be greatly improved by means of the controller array. In this way, the gray level and brightness of each controller are very good, the field scanning frequency is also appropriate, and then through the form of the controller array, a large control area is realized, and the LED display controller of the full-color super large screen with fine color can be realized.

The independent video LED system is completely out of the control of the computer, and can realize functions such as communication, video playback, data distribution, and scanning control. In order to achieve large screen, full color, high field frequency, the system uses the controller array mode, as shown in Figure 1.

The system can update the local data by the network server through the network interface (the Ethernet interface), and the video playing part decodes the data to obtain the video stream in the RGB format. Then, through the data distribution unit, the data is separately sent to different LED display controllers, and the controller displays the data provided by the playback unit to the full-color large-screen LED.

2 communication interface and video playback unit
The communication interface and video playback part of the system are implemented by ARM+uClinux. ARM (Advanced RISC Machine) is a general-purpose 32-bit RISC microprocessor architecture designed and developed by ARM in the UK. The design goal is to realize a miniaturized, low-power, high-performance microprocessor. As a stable and efficient open source operating system, Linux has been widely used in various fields, and uClinux is a Linux system designed specifically for the field of micro-control. It has a network interface protocol that can be reduced, small and complete. And interfaces, excellent file systems, and rich open source resources are being adopted by more and more embedded systems. The system uses the Intel XScale series PXA255 chip, which is compatible with the ARM v5TE instruction set. It uses ARM memory management and interrupt processing mechanisms, and has made some extensions on this basis, such as DMA controller and LCD controller. Due to the limited processing power of the ARM9, it is currently only used to play 320 x 240 pixels of video.

The data played by the system video comes from the SD Memory Card (Secure Digital Memory Card) in the system. There are two ways to update the data of the SD card: one is to update the data of the SD card with a computer; the other is to receive the data of the server through the network, and directly update the SD card by ARM. In addition, the player can also directly play MPEG-4 format data transmitted by the network. Since XScale does not provide a physical layer interface, if you want to implement network functions, you need to connect a physical layer chip. This system uses SMSC's high-performance 100M Ethernet controller LAN9118.

3 Video data distribution
Since the controller adopts the array mode, it is necessary to distribute the data provided by the video source, and correctly send data of different ranks to different controllers.

3.1 Data Distribution Unit Solution

The LED controller in this system has a gray level of up to 3×12 bits (up to 64G colors can be displayed) and a control area of ​​128×128 points. The data provided by the system playback unit is 320 × 240 pixels, so it needs to be broken down into 6 LED controllers to control (see Figure 1). Therefore, the RGB data provided by the PXA255 needs to be sent to the 6 controllers in three groups, and implemented as an FPGA. The scheme is shown in FIG. 2 .


The LCD interface sub-module receives the data and control signals of the PXA255 LCD interface, and the input data is corrected point by point and stored in the SDRAM. The field data is then divided into three groups of 128 lines each (the last group has only 64 lines, which is zero-padded by the bus scheduler for the consistency of the subsequent control boards), simultaneously transmitted, and then processed by the LED display controller.

3.2 Memory Allocation and Bus Scheduling

In order to facilitate the interface between the modules, the data synchronization of different clock domains is facilitated. The memory of the system adopts a two-level storage mode, that is, SDRAM is used as the main memory, and each module also has a corresponding FIFO as a cache. SDRAM has the advantages of large capacity, high bandwidth, and low price; however, the control is complicated, and there are multiple control and waiting cycles for each read and write. Therefore, in order to improve efficiency, the burst read and write method of increasing the address is usually used, and the data of any address cannot be read at any time like the SRAM.

This scheme adopts a completely dynamic memory allocation mechanism, that is, when each module requests, if it is not the same field data, it can be allocated a new memory, and once the data of the memory is no longer valid, the memory is released. Thus, each block of memory has its own attributes, whether the memory is in use, or free memory, and whether the current in-memory data is waiting in the queue being used, so the memory needs to be divided into three blocks. One of them stores the point-by-point correction parameters, one for storing the current field data and the other for storing the previous field data (ie, the data being transmitted). This requires that the data needs to be sent during a field synchronization period, and this requirement is fully achievable.

Bus scheduling is the core part of this module. It is necessary to accurately calculate the bus bandwidth occupancy and determine the depth of each part of the FIFO to ensure that each FIFO does not overflow or read empty.

The bus scheduler needs to schedule three blocks of memory, and maintains the first address of an offset address for each module, as well as an offset address count register. In order to facilitate the calculation of the offset address, two rows of physical data are stored in the SDRAM, and the excess is spared.

The arbitration algorithm of the bus scheduler is: the point-by-point correction parameter is the same as the priority of the corrected data writing to the SDRAM, and the bus is occupied in a first-come, first-served manner, and the bus occupancy is triggered by the pointers of the respective FIFOs. After a data is written to the SDRAM, it starts to be sent. It is necessary to sequentially read the data of the nth, n+128, n+256 lines to the data transmission FIFOs 0, 1, 2, and wait for the data transmission unit to start transmission.

3.3 LCD interface and point-by-point correction
The LCD interface of the PXA255 is configured as a smart panel. For the timing relationship, refer to the manual of the PXA255. Based on these timing relationships, the FPGA reads the data for further processing.

Since the parameters of the LED tube cannot be completely consistent during the production process, in order to obtain a good image display effect, the LED tube must be screened. This is also an important reason why LED screens are expensive.

Using point-by-point correction technology, the brightness of the LED can be adjusted point by point, and the brightness of the display is increased by a certain level, so that the purchaser can relax the brightness and color requirements of the LED, and the cost of LED procurement is also greatly reduced. . In addition, the point-by-point correction technology adopted by the system can modify the calibration parameters online, so that the LED screen can also modify the calibration parameters after being put into operation, compensate for the influence of the LED tube aging on the display effect, and improve the service life of the LED screen. Therefore, the point-by-point correction technique makes the LED module an ideal solution for the basic components of indoor and outdoor full-color displays.

The point-by-point calibration parameters are stored in the SD card. After the system is powered up, the ARM first transfers the data to the FPGA through the LCD interface (configured as GPIO at this time), and the FPGA stores it in the SDRAM. After that, the data input to the LCD interface can be corrected.

3.4 Data transmission

When data is transmitted, each line of data is transmitted as one frame, after a specific frame header is added. In order to reduce the number of buses, a serial bus is used, and each group of signals has four channels, which are source synchronous clock and serial data of RGB three primary colors. The signals are transmitted in the form of LVDS (Low Voltage Differential Signal). LVDS transmits data in a differential manner, with stronger common-mode noise rejection than single-ended transmission, enabling long-distance, high-rate, and low-power transmission. Altera's Cyclone II family of FPGAs provides easy access to LVDS through I/O configurations.

The transmission frame header consists of a 4-byte sync header + data current line number + ID number. Since the correlation of successive pixel values ​​of the image is relatively high, the pseudo-random code is used as the synchronization header, and the synchronization performance is relatively reliable. The current line number is used by the controller to determine whether a frame loss occurs, and the current data storage address is determined according to the current line number. Since each set of data is actually processed by two controllers separately (see Figure 1), a decision flag is needed to intercept different portions of the data. The ID number is the standard for different controllers to intercept the number of different columns in a row. The ID of the data is zero when sent.

4 full color LED display controller

The full-color LED display controller is responsible for receiving, converting and processing the serialized RGB three primary color signals, and transmitting the signals to the LED display screen in a certain regularity and manner. The controller directly determines the display effect of the display, and also determines the performance of the LED display. The structure of the controller is shown in Figure 3.


The architecture of the controller is similar to data distribution. It also adopts the secondary storage mode, which mainly includes data receiving, gamma correction and interleaving, scan control output, bus scheduling and SDRAM control.

4.1 Memory Allocation and Bus Scheduling

Since the data input field frequency and the LED scanning field frequency are usually not integral multiples, it may happen that the input field data ends, and the processing result of the field data (after gamma correction and interleaving) needs to be written into the SDRAM, and at this time, there is no scanning session. At the end, that area that is being read cannot be overwritten, and the data of the previous field has not been displayed or covered, so interleaved writing (ie, scanning readout) requires three partitions to be opened.

The bus arbitration algorithm is: the control output module and the write module adopt a first-come, first-served algorithm, and the read and write of the correction and interleaving process has the lowest priority, and can be suspended when the previous two applications are applied, only the current two are not When the bus is needed again, the right to use the bus can be assigned.

4.2 Data reception

In addition to the need for synchronous decision, serial-to-parallel conversion, the data receiving unit also determines which data in a row needs to be processed by the controller. The controller intercepts the data of the 128*ID~128*(ID+1)-1 column in each row, and increases the ID number by 1, and the other data is output as it is, and is sent to the next controller. Such a control method is more flexible and reliable than the commonly used dial switch method.

4.3 Gamma correction and interleaving

Gamma correction can make the LED display closer to the physiological characteristics of the human eye, and since the PXA255 outputs 8-bit data, the system needs to correct it to 12 bits, which greatly improves the contrast of the display.

Since the LED display controller adopts a bit-by-bit display method, the input data is organized differently from the data outputted to the LED display screen: the former is arranged by pixels, and the latter is organized by different numbers of pixel values.

4.4 Control output

The 12-bit data display time is (64, 32, 16, 8, 4, 2, 1, 1/2, 1/4, 1/8, 1/16, 1/32) * 128 * Tsclk, where Tsclk Is the serial shift clock. After the interleaving, the data display signals of different weights show different effective times, and the display effect can be achieved.

The bus scheduler writes the interleaved data to the FIFO of this module. A control signal for reading the FIFO is generated internally by the module and counted. The number of shifts and the weights need to be counted in the module to determine the effective time for issuing the latch signal and displaying the signal.

5 Conclusion <br>
Experimental results show that the system has good brightness, fine resolution (64G color), high field scanning frequency (about 400 Hz), and high pixel (320×240 points), which can be used in outdoor broadcast applications. The design adjusts the brightness point by point, which allows the purchaser to relax the brightness and color requirements of the LED. The cost of LED procurement is also reduced. From 8 to 12, the color level of the image is greatly increased, especially at low levels. The brightness area allows the image to be perfectly reproduced, while the Gamma correction makes the brightness change of the LED display more in line with the physiological characteristics of the human eye. In addition, in addition to receiving signals from the ARM, it can also receive data signals from the set-top box through the HDMI interface, which has broad market application prospects.

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