Fpga button control digital tube display

**Button and Digital Tube Display** A LED digital display (LED Segment Displays) is a device that consists of multiple light-emitting diodes (LEDs) arranged in an "8" shape. These LEDs are internally connected, and to activate the desired segments, you only need to connect the corresponding strokes and common electrodes. The most commonly used types have 7 segments plus a decimal point, while others may include additional features such as half digits, 1, 2, 3, 4, 5, 6, 8, 10, and more. Based on the connection method of the LEDs, these displays can be categorized into two types: common cathode and common anode. Understanding these characteristics is crucial because different types of digital tubes not only require different hardware circuits but also different programming approaches. Figure 2 shows the internal circuit diagrams for both common cathode and common anode digital tubes. Their illumination principle is similar, with the main difference being the polarity of the power supply. The available colors include red, green, blue, yellow, and others. ![Fpga button control digital tube display](http://i.bosscdn.com/blog/pI/YB/AF/pdtruARdd8AAC5YEX5feg260.png) Figure 1: This is a 10-pin 7-segment LED digital tube with a decimal point. ![Fpga button control digital tube display](http://i.bosscdn.com/blog/pI/YB/AF/pdtsyAFcLAAABWAJARZbg582.png) Figure 2: Pin definition. The following section describes the implementation of an FPGA-based program for controlling a digital tube display using buttons: ```verilog module key_led(clk_50M, key, duan_ma, wei_ma); input clk_50M; input [3:0] key; // Key code input output [3:0] wei_ma; // Digit selection signal output [7:0] duan_ma; // Segment code output wire [3:0] key; reg [7:0] duan_ma; reg [3:0] wei_ma; reg [3:0] key_temp; always @(posedge clk_50M) begin key_temp <= key; // Store key value case (key_temp) 4'b0111: duan_ma <= 8'b11000000; // Display '0' 4'b1011: duan_ma <= 8'b10010000; // Display '9' 4'b1101: duan_ma <= 8'b10000010; // Display '6' 4'b1110: duan_ma <= 8'b10110000; // Display '3' endcase end always @(posedge clk_50M) begin case (key_temp) 4'b0111: wei_ma <= 4'b0111; // Select digit position 4'b1011: wei_ma <= 4'b1011; 4'b1101: wei_ma <= 4'b1101; 4'b1110: wei_ma <= 4'b1110; endcase end endmodule ``` This module controls the digital tube display based on the key pressed. Each key corresponds to a specific segment code and selects the appropriate digit position. For static display of numbers 0–7, here's another module: ```verilog module led_0_7(clk, rst, dataout, en); input clk, rst; output [7:0] dataout; // Segment code output output [7:0] en; // Digit enable output reg [7:0] dataout; reg [7:0] en; reg [15:0] cnt_scan; // Scan frequency counter reg [4:0] dataout_buf; always @(posedge clk or negedge rst) begin if (!rst) begin cnt_scan <= 0; end else begin cnt_scan <= cnt_scan + 1; end end endmodule ``` This module provides a static display of digits 0 through 7 by setting the appropriate segment codes and enabling the correct digit position. It ensures stable and clear display of numbers on the LED digital tube.

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