Recently I learned the design architecture of ARM+FPGA. The communication between ARM and FPGA structure can be roughly divided into two types:
One is the case where the amount of data is small and the communication rate is not high. Consider using the SPI, IIC, etc. ARM has an associated SPI communication controller, etc., and it can be directly operated on the ARM side to the relevant SPI communication controller. The FPGA can be used as an SPI slave. According to the timing of the SPI protocol, the slave interface is written. This workload is not so large, so it is relatively easy.
The other is the case where the amount of data is large and the communication rate is high, and the parallel bus method is adopted. At this time, the FPGA can be used as an off-chip SRAM access of ARM. A dual-port RAM can be generated inside the FPGA. The output data bus leg is directly connected to the data bus of the ARM parallel bus. The address of the dual-port RAM end. The bus is also directly connected to the address bus in the parallel bus of ARM. In this way, the FPGA can read and write from the DPRAM side, and the ARM reads and writes from the other end of the DPRAM. Of course, other control signals for enabling or chip selection are needed. Here FPGA side is better implemented, and ARM side needs to develop SRAM (FPGA) driver, this has not been actually done, so it is not sure.
The parallel bus of NXP's ARM or LPC series is called the external address and data bus. It is controlled by EMC (external memory controller). By controlling the EMC register, data can be transmitted and received on the external address and data bus. If you use LPC series ARM plus a piece of FPGA, the key to realize their communication should be the control of this EMC register. I don't know if the data transceiver program written by this register group in a certain order can be called so-called driver. Great God explained.
TI's ARM or DSP has a GPMC (Universal Memory Controller), which is similar to LPC's EMC and is an excuse for TI's chips to communicate with external storage devices such as NORFLASH, NANDFLASH, and SRAM. We have the question of the upper one.
Samsung's S5PV210 has a set of parallel bus interfaces, called SROM, and also has a SROM controller that supports NORFALSH, NANDFLASH, SRAM, etc., which should be similar to the EMC of the LPC series. I can read and write to the external SRAM (FPGA) by operating this control register. I don't know if this is correct.
Another question is, if there is an operating system, is it not so simple to realize the communication between ARM and FPGA? In the absence of an operating system, I can only implement a certain control register operation, which is not feasible at this time? These are all to be understood in the future. After investigating for such a long time, I have never started to look for existing resources, write a program to do this communication, and I still don't understand it. If you really have to practice everything, you can understand it profoundly. There is an LPC2478 ARM plus FPGA board on hand, but there is no operating system or only UC/OSII. I don't know if there is any difference between ARM and ARM operating system such as Linux. Let's get started and do it.
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