Embedded basics
To do embedded system development, you often have to contact the hardware. Doing embedded development requires a certain understanding of digital circuits and analog circuits.
Only in this way can we deepen our research. Below we briefly introduce some hardware-related concepts in embedded development.
Bus
There must be a processor chip in the embedded system. In addition, there are other chips as external devices (hereinafter referred to as peripheral devices). These chips cooperate with the processor to realize the functions of the product. Complex products are often composed of a large number of chips. It is inevitable that we need to connect all the peripherals with the processor. The simplest is to connect all the peripherals to the processor with independent (note that independent) signal lines. This benefit is easy to understand. But the problem is: not feasible.
Because the processor chip needs to lead too many lines, it is not practical from the point of view of the production of the chip and the production of the product. In addition, the processor (here we assume that the processor is single-core, rather than multi-core) processing transactions on the microscopically serial, that is to say if you want to read and write to peripherals at a certain moment, it is only possible It is performed on one of a large number of peripherals, that is, multiple peripherals cannot be microscopically accessed by the processor at the same time.
It should be noted that the micro concept is proposed here to distinguish it from the macro. From a macro perspective, a single processor can have multiple tasks running at the same time, but these tasks are microscopically one by one (these will be used to describe the "one by one" here), multitasking Serial operating implementation is achieved by the operating system playing an important role.
Going back to our topic, it is not feasible to connect each peripheral to the processor with an independent signal line, and the processor will only access one peripheral in a single time. Can we use the shared signal line? Connect all the chips together? This is the origin of the bus concept. In layman's terms, if we have 10 families around us, in order for each of the 10 families to come and go between them, we don’t need to fix a separate (note that alone) way for every two families (if so, To repair 45 roads), it is possible to build a road, and then each home is connected with the road.
For the bus, we often say that the bus is the processor, and other peripherals are hung on the bus. There is a problem. We can only access one peripheral device on the bus each time. How do we distinguish between these peripheral devices? Like ours, we need to use addresses to distinguish each family. On the bus, we also use addresses to distinguish between them.
In this way, the bus is divided into two categories according to its function. One type is the address bus. The data on this bus will only flow from the processor to the peripherals, which is unidirectional. The other is the data bus, which is used to transfer data from the processor to the peripheral (write operation from the processor's perspective) or to transfer data from the peripheral to the processor (from the perspective of the processor It is a read operation. Obviously, the data bus is bidirectional. In other words, both the address bus and the data bus exist in our embedded system to connect all the chips that need to communicate with the processor.
The bus has a width, just as our road is divided into "three lanes" or "four lanes." We say that 32-bit processors mean that the data bus width is 32 bits, that is, "There are 32 cars that can run at the same time. "Obviously, the wider the width, the faster our processor speed will be, because we can access data from peripheral chips faster, which is why our computers have evolved to 64-bit." Similarly, the address bus is also wide, with a maximum width of 32 bits for a 32-bit processor.
The concept of the bus has, then the next question is, even if each peripheral has an address, where does this address go? Is it on a peripheral chip? If this is the case, then there is a problem. The address of each type of peripheral must not overlap. When two chips are required in the same product, the addresses of the two chips cannot be distinguished. There is a problem. Also, if this is the case, each peripheral must be completely connected to (for example, 32) data buses and listen to the data line to see if the processor is "calling" itself, which is very complicated.
In addition, the address may also be used up because of the increase in the type of peripherals. In general, the address can not be stored in the peripheral chip, then how to make the peripheral know, at this time it is the processor to change and thus need to read and write access? The answer is the Chip Select (CS) signal or the ENable signal.
Chip Select (CS or EN)
The chip select signal is a (but also a) notification signal to the peripheral chip, tells the chip "Hey, please open the door, I want to put some things in, or take something to go", here's only data It can't be a corn cob or something. There is a problem. Where does this source come from? Obviously, only from the processor. Is it also like a bus, where each chip shares a common line?
If so, it may be that the processor “opens the door†and all the chips will open the door. If the processor writes data, it may be that all chips are written with the same data. When data is fetched, each peripheral chip “tossed†data outwards, which will definitely cause a data bus collision because some chips “throw†1 on the bus and others “throw†0. The processor must be "crazy" because it does not know whether it should get 1 or 0.
Now that it is clear that all chip select signals cannot be connected together, only the chip select signals of each chip are independent. As mentioned earlier, the address bus, we use an address line with a peripheral chip? Still using other methods. If you use an address line to connect a peripheral chip, you may only be able to mount up to 32 chips, which is obviously not acceptable.
In fact, in reality, a 32-bit number is used to represent the address of a peripheral chip. For example, 1 may represent chip A, and 6534 may represent another chip B, and so on. From this point of view, theoretically we can express 2 to the 32th power (4294967296) devices, in theory, because some devices take up a large number of addresses. Now that there is a problem, if you convert the 32-bit address bus into a chip select signal for the chip? This requires the introduction of the concept of a decoder.
decoder)
The decoder converts a data into a signal on a signal line, such as a 3/8 decoder, which can convert a bit width of 3 bits into 8 (2 to the 3rd power) completely independent signal lines. When the binary 011 is written to the data side, the third root of the eight lines corresponds, and when the binary 111 is input, the corresponding one of the eight lines is the last one. With the decoder, the processor's address line is simplified, as long as the 32 address lines plus the external decoder, you can access a large number of peripheral chips. We have already solved the problem of the selection of external devices. Now we must look back at the data bus.
In embedded systems, the data bus of all chips can be understood to be directly connected. The word "understandable" was used because in order to increase the bus's load capacity, bus drivers were added. To understand, let's look at tap water in our lives. For example, in Beijing, theoretically all water pipes may be connected, but in order to increase water pressure, there may be many small water stations to increase water supply pressure. It is unlikely that all tap water in Beijing will come from a water plant.
Now that all data buses are connected, there may be problems. When writing data to an external device, the processor first sends the address of the target peripheral to the address bus. The chip is then converted into a signal by the address decoder. The chip select signal is sent to the target peripheral, and the target peripheral receives this signal. , Open the door. Next, the processor will transfer the data to the peripheral to the data bus. Since only the target peripheral chip has opened the “gateâ€, the data will only enter the target peripheral, and other peripherals will not receive anything. To. Very good! The processor should write data out without problems. Let's take a look at it.
If you read, because the data is sent from the peripheral to the processor, although we use the same method to open the "gate" of the target peripheral, but at this time, other peripherals are also on the data bus, they may be in 1 may also be at 0, does it affect the processor to read the target peripheral data? Of course not, but we have to introduce another concept: high impedance.
High impedance
Obviously, when the processor reads data from the target peripheral, we hope that the data buses of other unselected chips will not affect the data to be transmitted by the target peripherals. What should we do? In fact, when the chip is not selected, its data bus is in a high-impedance state.
The so-called high-impedance state, we can understand that this pin is disconnected inside the peripheral chip, so that obviously will not have any effect on the processor to read data from the target peripheral. We say that when a chip is not selected or is not enabled, its data bus must be in a high-impedance state. In front of the "door" to open and close analogy, what does the "door" mean? Refers to the peripheral data bus. The role of the chip select signal is to control the connection or disconnection of the peripheral data bus from the processor's data bus.
drive
Whoever puts the data on the bus, we say who is the driver of that moment. That is, when the processor writes data to a peripheral, it drives the data bus, and when the processor reads data from the target peripheral, the target peripheral drives the data bus. For the address bus, the address bus is always processor-driven because it is only possible to write from the processor to the target peripheral. When a chip is not selected, we say that it does not drive the data bus.
Three-state door
We mentioned earlier that the data bus of the peripheral chip is in a high-impedance state when it is not selected. When it is selected, its level may be high (1) or low (0). In this way, we say that the data bus of the peripheral device has its tri-state gates, that is, there are high, low, and high impedance states, and three states.
Level validity
We learned earlier about what is a chip select signal and also talk about tri-state gates. It should be pointed out that the chip select signal is usually not a tri-state gate. It only has two states, namely high level or low level. We also said earlier that the chip select signal is used to “open the doorâ€, and the chip select signal has high and low levels. In the end, the high level means “open the doorâ€? Still low?
For this problem, we say that if a level indicates “opening†for a chip select signal then it is the effective level of this signal. For example, for a chip select signal, if the low level means "open the door," then we say that the chip select signal is active low. Although we use the chip select signal to explain the validity of the level here, there are problems with the effectiveness of many signals. For example, the read and write signals we will discuss later have validity problems.
Timing
In the foregoing, we mentioned that when a processor wants to write data to a peripheral chip, it needs to first put the address of the peripheral to be accessed on the address bus. Then, the decoder converts the data on the address bus to chip select. Signals, chip select signals enable the target peripheral chip, and then the processor writes data to the data bus to complete a write operation. Obviously, the data on the address line must remain for a period of time before the processor writes data to the data bus, otherwise the decoder cannot assert the chip select signal for a long time.
When the data write operation is complete, the processor does not need to guarantee that the address on the address bus is valid. We can see that this series of operations has a strict chronological order. This is called timing. The time sequence describes the “regulation†of the interaction signal between the processor and the external device. We only operate in accordance with this “procedure†to ensure normal communication between the processor and the external device. This is like the traffic light on our road. If our pedestrians and vehicles do not follow their instructions, an accident will occur. In general, timing diagrams are used to describe the signal "procedures" for communication between chips.
ADDRESS represents the address bus, DQ represents the data bus, CE is the chip select signal, and it is active low, and its width must be guaranteed to always be valid during read operations. Learning to see the timing diagram is very helpful for doing embedded system development, because we have to deal with the chip inevitably.
In the timing diagram, a lot of time requirement information is usually identified. When writing the startup code, it needs to initialize the chip select address register and read/write timing of each address space. The timing configuration is based on the time requirement of the peripheral chip. This is a very important part of the chip manual. When there are multiple peripheral chips in one address space, we need to consider the time requirement of the slowest peripheral chip among them, otherwise some chips will not work properly.
Read signal
When a processor needs to read a signal from a peripheral chip, in addition to generating a chip select signal, it also needs to tell the peripheral chip that this is a read operation rather than a write operation. This is achieved by reading the signal.
Write signal
In front of reading the signal, I think it is not difficult to understand the signal for writing, this signal is used to tell the peripheral chip, which is an operation to write data to the peripheral chip.
I/O port
As mentioned earlier, peripherals (chips) are now the time to classify peripherals. In general peripherals are divided into two categories, one is a memory peripheral, and the other is a non-memory peripheral, the latter often referred to as I / O devices, where the I / O is a shorthand for Input / Output, ie input Output. It can be seen that the I/O peripheral is a very broad concept. For memory peripherals, the feature is that it takes up a contiguous piece of space. For example, SDRAM memory is a memory peripheral. If its capacity is 8 Mbytes, its occupied address space will be 8 Mbytes.
Unlike memory peripherals, the I/O peripherals typically use very few addresses. For example, an I/O peripheral may have multiple control registers. These control registers are multiple I/O ports (addresses) from the processor. Writing data to this address is writing data to the corresponding register of the peripheral device. It can also be read. For example, a serial chip may have multiple registers, one for querying the status of the chip, one for setting the chip's function, another for reading the data received by the chip from the serial line, and finally, a method for Write data to the chip to send data to the serial port. For this serial chip register, from the processor point of view, all are independent I/O ports.
I/O ports have read and write problems. Some ports are read-only. Some ports are write-only. Other ports are readable or writable. Their read/write performance is determined by the registers of the peripheral chip. Determined to be found in the chip's data sheet. It should be noted that some memory peripherals also have I/O ports to control them. Judging from the name of the I/O port, for the processor, it is a generic term for an interface that reads data from outside or outputs data outside.
Break
Interrupt from the hardware point of view is a signal line that can generate high and low levels, but understand it needs to be from the perspective of the processor. We said that, from a microscopic point of view, the work done by the processor is in order, and its processing of the program can only be the execution of one instruction and one instruction. If there is a need for access to a peripheral chip, and it is possible to issue read and write commands from the processor, since the peripheral is usually much slower than the processor, the peripheral chip needs some time to prepare the required data. In this case, if the processor keeps waiting for the return data of the peripheral chip to execute the subsequent instructions, it will consume precious time, which can be used for other tasks completely.
Don't forget that processors are often multi-tasking at the macro level. Tasks are the scheduling units provided by the operating system. When a task blocks due to data waiting for the peripheral chip, we can switch to another task, thereby improving processing efficiency. This has a problem. When the processor handles another task, if the data of the peripheral chip is good, if it tells the processor? It is through the interrupt signal. The high and low levels of the interrupt signal can be used to indicate whether an interrupt requires the processor's attention to handle a particular event (eg, an event where the peripheral data is ready).
From this point of view, the introduction of interrupts can greatly improve the efficiency of the processor. In order to use the interrupt on the processor, we need to initialize the interrupt controller of the processor at first, such as installing the required interrupt service program or calling it the ISR (Interrupt Service Routine), and then turning on the interrupt mask bit. The following operations need to be done in the interrupt service routine:
1. Read from a peripheral or write data to a peripheral. Reading or writing usually requires reading the peripheral's interrupt status register.
2. Clear the peripheral interrupt signal. We know that the interrupt signal is driven by the peripheral chip. In order to tell the peripheral chip that the processor has finished the required work, the processor needs to inform the peripheral chip in a certain way. This method is to write a data to a bit in the register of the peripheral chip. For example, it may be written as 1 to clear the interrupt, or may be written to 0 to indicate the clear interrupt. This is usually available in the peripheral data sheet. Checked. When the peripheral device receives a clear interrupt request from the processor, it will drive the interrupt line to disable it. For example, the interrupt line of a peripheral means that when it is low, it means there is an interrupt, and changing it from low to high means that the drive is invalid.
3. Clear processor interrupt signal identification. The processor often also saves whether the external interrupt signal has occurred. When we have processed the interrupt of the peripheral chip, we also need to clear the identifier on the processor to prepare for the next interrupt. It should be noted that the clear peripheral interrupt must occur before the processor interrupt identifier.
There is also a triggering issue with interrupts. There are two trigger modes, one is level triggering and the other is edge triggering. Level triggering refers to whether the level is high or low, indicating whether the peripheral has an interrupt, and the edge trigger can be expressed by rising or falling over the level of the interrupt line. Obviously, there are two edge trigger modes. One is that the interrupt line goes from low to high, which we call the rising edge trigger, and the other is that the interrupt line transitions from high to low, which we call the falling edge trigger. In general, the trigger modes for interrupts are level trigger, rising edge trigger, and falling edge trigger. One of the important steps in interrupt handling during level triggering is set.
multimeter
Multimeter is usually used to check the level of the level, the size of the resistance, etc., is one of the commonly used and indispensable tools. In the development of embedded systems, we often use digital multimeters.
Level
In the digital circuit, it is divided into high level and low level, which are represented by 1 and 0 respectively. The pins of a digital circuit always have a level, either high or low, or either 1 or 0 (in fact, there is another state).
Oscilloscope
In the development of embedded systems, we inevitably deal with peripheral chips. When debugging the driver, in addition to the need to fully understand the chip's data sheet, and in the process of software height, we also need to see whether we expect the signal level to occur on the chip. For example, when writing a driver, we need to write the I/O port to operate the peripheral chip. When writing the corresponding I/O port, we know that the chip select signal of the corresponding chip should be valid. Sometimes, we need to verify. Whether it happened as expected, this requires the use of an oscilloscope. A typical oscilloscope can simultaneously observe the signal states of two signal lines.
Oscilloscopes provide certain functions, such as setting the signal capture method. An important parameter of an oscilloscope is its acquisition frequency. According to the Nyquist acquisition theorem, if we want to use an oscilloscope to view a signal with a frequency of 100 MHz, then its sampling frequency must be at least twice that of 200 MHz. Someone may ask: Why don't you use a multimeter to see it? Because the multimeter's acquisition frequency is very low, you can't collect very fast signal changes.
logic analyzer
Simply put, a logic analyzer is an oscilloscope with many signal channels. Through the logic analyzer, we can see the data on the address bus and data bus. The logic analyzers provide some programming ability to program when to start collecting data on the bus.
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