FPGA (Field Programmable Gate Array) is a highly integrated programmable logic device that allows for system-level programming. By loading different configuration data, it can implement various logic functions. Using FPGA in the design of electronic systems offers significant advantages, such as a short development cycle and ease of modification. This makes it particularly suitable for scientific experiments, prototype development, and small-scale production of electronic products.
In this paper, we use Max+Plus II, an ETA tool software, to design a taxi meter using FPGA technology. The designed taxi meter can display both the distance traveled by the taxi and the fare payable by passengers in decimal format. This system has practical value and demonstrates the application of FPGA in real-world scenarios.
**1 System Design Requirements**
The taxi meter must display both the mileage and the fare, with mileage accurate to 0.1 km and fare accurate to 0.1 yuan. The display should be in decimal form. According to the charging standard: the base fare is 6 yuan for the first 3 km. For distances between 3 and 7 km, the rate is 1.6 yuan per kilometer. For any distance beyond 7 km, the rate increases to 2.4 yuan per additional kilometer.
**2 System Design**
The system can be built using discrete components or a single-chip microcontroller, but using FPGA provides distinct advantages, such as a shorter design cycle and easier modifications. With the rapid development of programmable logic devices and EDA tools, more and more electronic systems are now being designed using FPGAs. Once the system reaches a large-scale production stage, it can be easily converted into an ASIC design.
In this project, we use MAX+plusII, an EDA tool, to design the taxi meter. The system is developed using a combination of Verilog HDL and schematic design, with each module eventually integrated into the complete system.
The mileage is generated by the rotation of the taxi’s wheel and counted by a counter. Assuming one pulse is generated every 2 meters, a new pulse signal is output every 50 pulses, representing 100 meters. This 100-meter pulse serves as the clock signal for the mileage counter, which is implemented using a 50-meter counter.
The mileage counter is a three-digit BCD counter capable of displaying up to 999. The first two digits represent integers, while the third represents a decimal, allowing a maximum mileage of 99.9 km. Each time the counter advances by 1 km, it generates a 1-km pulse signal, which is used to calculate the fare.
The core of the system is the billing mechanism. A BCD adder is designed to calculate the total fare based on the starting price and the charging standards. The unit price is determined according to the distance traveled and is generated using Verilog HDL. The overall block diagram of the system is shown in Figure 1.
**2.1 Unit Price Generation Module**
The Verilog HDL code for the unit price generation module is as follows:
[Image of Verilog HDL source code]
The input signals "bai" and "shi" represent the two-digit integer mileage from the counter. The output "jia" represents the unit price in three-digit BCD format. When the mileage is within 3 km, "jia" is 0. Between 3 and 7 km, "jia" is 016 (1.6 yuan), and beyond 7 km, it becomes 024 (2.4 yuan).
Using Verilog HDL allows for easy updates if the billing rules change, making it far more efficient than modifying hardware circuits.
**2.2 Three-Digit BCD Adder**
A three-digit BCD adder is used to sum the cost. The result is displayed in decimal form, with the first two digits as integers and the third as a decimal, allowing a maximum of 99.9 yuan. The adder is constructed by cascading three one-digit BCD adders.
Each BCD digit consists of four binary bits. When adding, if the result exceeds 9, it must be adjusted to produce the correct BCD output. Here is the Verilog HDL code for the BCD adder:
[Image of Verilog HDL source code]
The simulation waveform and symbol of the BCD adder module are shown in Figures 2 and 3, respectively.
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