FPGA (Field Programmable Gate Array) is a high-density programmable logic device that allows for system-level programming. It can implement various logic functions by loading different configuration data. Using FPGA to design electronic systems offers advantages such as a short development cycle and easy modifications, making it ideal for scientific experiments, prototype development, and small-scale production of electronic products.
In this paper, the Max+Plus II tool from ETA is used to design a taxi meter using FPGA technology. The system is capable of displaying both the distance traveled by a taxi and the fare due to passengers in decimal form, making it highly practical and applicable in real-world scenarios.
**1. System Design Requirements**
The designed taxi meter must display the mileage and the exact fare payable by passengers. The mileage should be accurate to 0.1 km, and the fare should be displayed in decimal format with precision up to 0.1 yuan. The pricing structure is as follows: a base fare of 6 yuan for the first 3 km. For distances between 3 and 7 km, the rate is 1.6 yuan per kilometer. For every additional kilometer beyond 7 km, the cost increases by 2.4 yuan.
**2. System Design**
The system can be built using discrete components or microcontrollers, but the use of FPGA provides significant benefits such as a shorter design cycle, easier modifications, and flexibility. With the rapid advancement of programmable logic devices and EDA software, more and more electronic systems are being developed using FPGAs. Once a system reaches a large production scale, it can be easily converted into an ASIC design.
In this project, the MAX+Plus II EDA tool is used to design the system. The approach combines hardware description language (Verilog HDL) with schematic design to create individual modules, which are then integrated into the full system.
The taxi meter displays the distance traveled, which is generated by the rotation of the wheel and counted by a counter. Assuming a pulse is generated every 2 meters, a new pulse signal is output every 50 pulses to represent 100 meters. This signal acts as the clock for the mileage counter.
The mileage counter uses a three-digit BCD counter, capable of displaying up to 99.9 km. Each time the counter increments by 1 km, it generates a 1 km pulse signal, which is used to calculate the fare.
The core of the system is the billing mechanism. A BCD adder is designed to compute the total fare based on the starting price and the distance traveled. The unit price is determined according to the billing standards and implemented using Verilog HDL. The overall block diagram of the system is shown in Figure 1.
**2.1 Unit Price Generation Module**
The Verilog HDL code for the unit price generation module is provided below. The input signals `bai` and `shi` represent the two-digit integer mileage from the counter. The output signal `jia` represents the unit price in three-digit BCD format, where the first two digits are integers and the last digit is a decimal. When the mileage is within 3 km, the price is 0 yuan; between 3 and 7 km, it is 1.6 yuan; and beyond 7 km, it is 2.4 yuan.
Using Verilog HDL allows for easy modifications when the billing rules change, offering much greater flexibility compared to hardware circuit changes.
**2.2 Three-Digit BCD Adder**
A three-digit BCD adder is used in the system to calculate the total fare. The result is displayed in decimal format, with two integer digits and one decimal digit, allowing a maximum display of 99.9 yuan. The adder is constructed by cascading three single-digit BCD adders.
Each BCD digit consists of four binary bits. When adding, if the result exceeds 9, it must be adjusted properly to ensure correct output. The Verilog HDL code for the BCD adder is shown below, along with simulation waveforms and module symbols in Figures 2 and 3.
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