Basic principle analysis of master-slave sr trigger

The following figure shows the main circuit diagram of a master-slave SR flip-flop.

Figure 1: Master-Slave SR Flip-Flop Circuit

**Working Principle:** **(1) S = 1, R = 0** When CP is high (CP = 1), G3 and G4 are disabled, so the output remains unchanged. The main trigger allows G8 and G9 to open, resulting in an output of Q = 1. As CP transitions from 1 to 0, G7 and G8 are disabled, keeping the main trigger’s output in its previous state. The slave trigger then updates its output based on the main trigger, setting Q = 1 and Q̅ = 0. When CP is low (CP = 0), both the main and slave triggers remain in their current states. When CP rises again from 0 to 1, the slave trigger is blocked, and the output remains unchanged. **(2) S = 0, R = 1** During CP = 1, G3 and G4 are disabled, so the output remains stable. The main trigger activates G8 and G9, leading to an output of Q = 0. Upon CP transitioning from 1 to 0, G7 and G8 are disabled, maintaining the main trigger’s output. The slave trigger then updates accordingly, resulting in Q = 0 and Q̅ = 1. When CP is low, both the main and slave triggers stay in their current states. When CP rises again, the slave remains in its last state. **(3) S = R = 0** In this case, the main trigger retains its previous state. When CP transitions from 1 to 0, the slave trigger also remains unchanged. **(4)**

Constraint: SR = 0

In summary, the operation of the master-slave SR flip-flop shown in Figure 1(a) occurs in two steps. First, when CP transitions from 0 to 1, the main trigger receives input signals and changes its state. During this time, the slave trigger is blocked, so its output remains unchanged. This phase is known as the preparation stage. Second, when CP transitions from 1 to 0, the main trigger becomes inactive, while the slave trigger is activated. It captures the current state of the main trigger and updates its output accordingly.

Figure 2: Working Waveform of SR Flip-Flop

During each cycle of the CP signal, the flip-flop only changes its output at the falling edge of the clock. This method of triggering is called pulse-triggering. As a result, the flip-flop avoids unintended state changes. Figure 2 illustrates the operating waveform of the master-slave SR flip-flop. In Figure 1(b), the small circle “〇” at the CP terminal indicates that the flip-flop is triggered by the falling edge of the clock signal.

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There are five types of main board power line interface, and different external devices correspond to different interfaces. Different interfaces and their connecting pins are also different. For example, the pin of the main power supply is 24 pins, and the hard disk drive is 5 pins.

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