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Abstract The audio encoder in the high-definition television source coding system based on ADSP2187 processor is designed and implemented. The encoder consists of real-time encoding and PES packing. The real-time encoding completes the encoding compression of stereo digital audio. The compressed stream conforms to the ISO/IEC11183-3 MPEG-2 standard and also receives the Dolby AC-3 ES stream input. PES package completes PES packaging of MPEG-2 and AC-3 ES streams. The working principle and design idea of ​​the encoder are described in this paper. The hardware structure of the encoder is described and the timing of the hardware design is analyzed.Keywords : audio encoder; ADSP2187; PES packaging
The MPEG-2 audio standard is based on the MPEG-1 audio standard. MPEG-1 hears signal-related coding noise at low data rates, and MPEG-2's outstanding contribution to audio quality at low data rates, including multi-channel stereo (surround) and multi-language program. The MPEG-2 audio standard has been widely used, and audio coding in high definition television is a hot spot in these applications [1~3] .
The audio subsystem of the high definition television includes audio encoding/decoding functions between the audio input/output and the transmission subsystem. An audio program source is encoded by an audio encoder and generates an audio elementary stream (ES stream). The transport subsystem converts the ES stream data into a PES (Packetsized Elementary System) packet, and then further converts it into a transport packet. . The transmitting subsystem transforms the transport packet into a modulated signal for transmission to the receiver. The audio encoder in the high definition television source coding system designed in this paper consists of real-time audio coding and PES packing and transmission. Real-time coding mainly uses the MPEG-2 algorithm [4] , and the encoder system also takes care of Dolby AC-3 coding [5,6] . The hardware core of the real-time implementation of the MPEG-2 encoding algorithm is implemented by AD's AD-SP2187 [7] , and the AC-3 encoding is done by Dolby DP569 provided by Dolby. Therefore, the system includes MPEG-2 encoding circuit and PES packing circuit in hardware design, and AC-3 encoder outputs PES packing circuit of ES stream.
1 audio coding system design
The audio encoder design of HDTV requires encoding compression of stereo digital audio under the control of the main control unit. The compressed code stream conforms to the ISO/IEC11183-3 MPEG-2 standard and can receive Dolby AC-3 ES. The stream is input, and the PES packet of the MPEG-2 and AC-3 ES streams is completed, and the audio PES stream is output to the multiplexer. Figure 1 is a schematic block diagram of the system.
The ES stream of the digital audio input and AC-3 encoded output in Figure 1 is compliant with the AES/EBU standard. The encoder output is an audio PES stream, and the PTS (Presentationtime stamps) value used by the PES packet is provided by the multiplexer. The master unit controls the encoder to work.
1.1 Hardware Design of Audio Coding System The hardware structure of the audio coding system is shown in Figure 2.
The whole system consists of audio receiver CS8412, sampling frequency converter AD1890, encoder core ADSP2187, high speed FI-FO, dual port RAM and EPLD device. Among them, CS8412 can automatically separate the left and right channel clocks, audio data and data corresponding to the input digital audio. The sampling frequency converter AD1890 receives the CS8412 separated clock and data and converts the sample rate to the 44.1 kHz or 48 kHz required by the encoder. The audio data after the sampling frequency conversion is completely encoded in the ADSP2187. The details of the coding are described in [4]. The ES stream data after the encoding is completed is output to the EPLD to complete the PES packaging. In order to match the output data with the timing of the packet information added in real time, a high-speed FIFO is used as a buffer between the two in the design. In addition, in addition to completing the ES stream packaged into a PES stream, the EPLD also completes the design of all interface logic of the hardware system.
When the data exchange between the main control unit and the ADSP2187, and initialization, the main control unit loads the encoding program to the ADSP2187 through the dual port RAM.
1.1.1 Design of the System Clock Circuit Since the sampling frequency input to the audio encoder must be locked to the 27 MHz system clock, the 27 MHz system clock must be used to generate the sampling frequency required for the AD1890 to operate. At the same time, DSP system design belongs to high-speed circuit design, and must consider signal integrity, delay consistency and other issues. The various signal clocks on the entire system board should be generated by the same clock source as much as possible, so the operating main clock (16 MHz) of the AD1890 is also generated by the 27 MHz system clock conversion. A phase-locked loop system consisting of two phase-locked loop devices, the AV9110, an AV9170, and an EPLD, is used to implement a 27 MHz clock conversion that produces a 16 MHz clock and a 48 kHz sampling frequency.
In the design of the phase-locked loop system, the AV9170 is used to multiply the 27MHz system main clock. The multiplied clock signal is divided by E-PLD to generate a 2 MHz clock, and then the 2 MHz clock is multiplied by another AV9170. Produces both 32MHz and 16MHz clocks. The 16 MHz clock acts as the master clock for the AD1890 to operate. The 32 MHz clock is programmed by the AV9110 to produce a 24.576 MHz frequency that is divided by 512 in the EPLD to produce the 48 kHz sampling frequency required by the AD1890, while also ensuring that the frequency is 27 MHz. The clock frequency is synchronized.
1.1.2 Design of the data channel At the same time as the DSP real-time encoding, the completed code needs to be output in real time. Since the computing speed of the DSP is on the order of MIPS, it is necessary to add a level 1 cache between the DSP output data and the real-time packaging. Asynchronous FIFO is the best choice for this function. IDT7206 is selected as the cache device in the design. During operation, the DSP keeps writing data to the FIFO until the FIFO is half full, at which point a read signal is sent to the FIFO. After reading a fixed length (such as a frame) of data, the read signal is disabled, and then the state of the FIFO half full flag is judged until the next half full occurs, and then the signal is read to the FIFO. It should be noted that the read signal period of the FIFO must be faster than the DSP write cycle, otherwise the above work mode is not established.
1.2 PES packet design The basic code stream of the audio is to be converted into a variable length data packet (PES) before being processed by the transport layer. The header of the PES packet contains a start code prefix and an identifier ID of the stream for identification. The elementary stream transmitted by the PES, in addition to the packet length and a number of optional fields, the most important of which is the display time (PTS), which occurs at the beginning of the packet's audio compression data. The audio encoder's PTS value is provided in real time by the system multiplexer, which is a 33-bit counter driven by a 27 MHz clock, as shown in Figure 3.
In Figure 3, DCLK is the 27 MHz system clock, DD is the serial PTS value, the data high is first, and DVLD is the valid signal corresponding to the PTS value. The rising edge of the 27 MHz clock corresponds to the period of stability of the data . The PTS value of 33 bits is transmitted each time, and the repetition frequency is 90 kHz. After the transfer system starts working, the serial data is converted to parallel by the shift register, and the PTS value is latched by the frame sync signal. After the PES is packaged, the audio frame start signal, the data clock, and the packed data are output to the multiplexer system. Figure 4 is a block diagram of the system structure of PES packaging.
When encoding, the DSP adds 16-bit header information before each audio frame. This header information can be used as a synchronization signal starting from one frame. Therefore, when playing a PES packet, the header information is first searched to generate a frame synchronization signal for PTS latching. Figure 5 shows the timing simulation of PES packaging, which is completed by VHDL programming and implemented by Altera's MAX7256.
Figure 5 AD[7. . When the value of 0] is 0xFFFDC400, it indicates the information of the frame sync header. When the string is searched, the head search signal CN is generated at the position corresponding to the data. In order to obtain the real-time PTS value, starting from the CN flag, counting one frame, using the counted carry signal as the frame synchronization signal AVLD, since the frequency of the audio PTS is refreshed at 90 kHz each time, that is, the change of the audio PTS value Relative to the system clock frequency is slow, so before each package output, using AVLD to sample and latch the PTS value that has been converted to parallel data can guarantee its real-time performance. When the AVLD is valid, it is output to the data bus AD of the multiplexer [7. . On the 0], a total of 14 Bytes of PES packet information values ​​are inserted, including the PTS value of the real-time input latched by the AVLD. In order to ensure that the audio data of the encoded output is not lost, when the PES packet information is inserted, the read signal of the FIFO is prohibited so that the audio data follows the packet information data, so that a complete audio PES packet is packaged.
The AC-3 coded output packing design principle is similar to that of MPEG-2, but it is more complicated when searching for the header, because the frame header information output by AC-3 encoding is not unique in one frame of data, while searching for the header. The frame length needs to be counted. If the frame length between the information words searched for two frames before and after is fixed, it means that the correct header information is searched, otherwise it is a pseudo information word. In addition, the output of the Dolby encoder DP569 is a burst mode. In one frame of data, the effective data is concentrated in the front part, and the rest are all zero. Specifically, in the output one frame, there are a total of 9 830 400. With one bit clock, only 25% of the clocks are valid data for AC-3. In the valid data, the AC-3 encoded data is in the upper 16 bits of the valid data word (32 bit), which requires the lower of each valid data word in addition to the effective data extracted from one frame. The bit is removed.
3 Conclusion
This paper discusses the hardware design and implementation of a high definition television audio encoder based on the ADSP2187 processor. In addition to providing high-quality encoding conforming to the ISO/IEC13818-3 MPEG-2 audio standard, the encoder also completes the PES packaging design of MPEG-2 and AC-3 ES streams, and multiplexes audio and video compression data in the multiplexer. The design has been simplified. Through subjective test experiments, the sound recovered after MPEG-2 and AC-3 decoding is close to the sound quality. The audio encoder is now used in the HDTV source encoder device of the National Digital Television Test Zone.
references
1 Painter T, Spanias A. Perceptualcoding of digitalau-dio [J]. Proceedings of the IEEE, 2000, 88(4): 451-504
2 Hoekstra E. Design and implementation ofa DSPbasedMPEG-1 audio encoder [J]. IEEE Transactions onConsumer Electronics, 1999, 45(1): 1-35
3 Kim Sung-Youn. A real-time implementation of the MPEG-2 audio encoder [J]. IEEE Transactions on Consumer Electronics, 1997, 43(3): 593-597
4 ISO/IEC International Standard 13818-3 [S]. CodingofMoving Pictures and Associated Audio Information, IS, 1995
5 DigitalAudio Compression Standard(AC-3)[S]. Unit-ed States Advanced Television System Committee (ATSC), A/52, 1995
6 Liu Xiaohua. Research and simulation of Dolby Digital audio compression technology [J]. Electroacoustic technology, 1998, 2: 2 ~ 7
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