· The new DSP architecture takes into account the need for control flow processing and digital signal processing for high-end smartphone, machine communication and wireless connectivity chip design
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· Scalable VLIW/SIMD architecture supports fixed-point and floating-point operations for unparalleled performance and energy efficiency
Introduce innovative modem architecture design to better integrate DSP, coprocessor, hardware accelerator, memory and system interface design
· The new CEVA-X series multi-RAT multi-carrier PHY control processor series for 2G/3G/4G/5G modems, CEVA-X4 is the first product
21ic News CEVA has introduced a new CEVA-X DSP architecture framework that redefines the performance and energy efficiency of control and data plane processing in baseband applications. With CEVA's deep accumulation in baseband processors (to date, more than 6 billion devices have built-in CEVA processor technology), the new CEVA-X architecture can handle increasingly complex baseband designs for a wide range of applications. Including LTE-Advanced physical layer control, machine communication (MTC) and wireless connection technology.
The new CEVA-X uses a scalable VLIW/SIMD architecture, up to 128-bit SIMD, variable pipeline length and support for fixed-point and floating-point operations. Compared to the previous generation CEVA-X, the new CEVA-X can provide more than 2 times the DSP performance, while the power consumption is 50% lower. The architecture also includes a dedicated 32-bit Zero-Delay Instruction Set Architecture (ISA), 32-bit hardware division and multiplication, dynamic branch prediction, and ultra-fast context switching to provide efficient control processing for modern baseband design requirements.
CEVA-X4 – Multi-RAT PHY Control Processor
The CEVA-X4 is the first core based on the new CEVA-X DSP architecture, targeting the most complex workloads in multi-RAT multi-carrier P physical layer control processing in 2G/3G/4G/5G baseband.
Mike Demler, senior analyst at Linley Group, commented: "Because the industry uses LTE Advanced Pro and is expected to achieve 1Gbps cellular download speeds, the current modem architecture will need to be fully innovated to meet today's stringent performance and power constraints. CEVA leverages this new baseband processor architecture to efficiently combine its high-performance DSP with real-time control to handle the entire baseband system to address this need. In addition, CEVA-X4 utilizes its advanced features such as parallel processing. Up to 5 carrier components provide customers with a roadmap to 5G."
The CEVA-X4 is designed to address the three most critical challenges facing next-generation modem designs:
· Efficient control processing: For multi-carrier aggregation, L1 PHY control processing is significantly increased. For example, processing up to 5 carrier components in parallel and sequentially processing multiple PHY control tasks on multiple carriers requires a new generation of Rel-13 LTE Advanced Pro modems.
· Powerful DSP processing: Significantly improved DSP performance to support heavy LTE workloads, including channel-by-channel measurement, correction and decoding, and other RAT standards.
Advanced system control: In order to handle multiple accelerators, DSPs, and coprocessors in the system with lower latency constraints, complex system scheduling and data communication management is required.
To address these challenges, the CEVA-X4 combines a unique set of baseband optimization features and functions in an efficient manner. The 128-bit wide VLIW/SIMD processor has 8 MACs in 4 identical Scalar Processing Units (SPUs). It has a 10-stage pipeline and operates at 1.5 GHz using a 16-nm process to achieve 16 billion operations per second (GOPS). Efficient control features of the processor include integer pipeline, full 32-bit RISC ISA with hardware division and multiplication, and branch target buffer (BTB) with a CoreMark / MHz score of 4.0, the most mature internal DSP used in smartphones today. 60% higher (per thread).
For system control, the CEVA-X4 utilizes the innovative CEVA-ConnectTM technology to coordinate the entire PHY system, including DSP, coprocessor, accelerator, memory and system interface, providing a holistic approach to modem design. It is equipped with a dedicated hardware coprocessor interface that introduces automatic data and control communication management mechanisms without software intervention. Its memory subsystem supports advanced non-blocking 2-way or 4-way Cache mechanisms with hardware and software prefetch capabilities.
Michael Boukaya, vice president and general manager of CEVA's wireless business unit, commented: "Building a modern baseband is very complex and requires a new approach to solving the bottleneck of system design. CEVA-X4 helps empower customers to develop the most simplified multimode modem system architecture to Achieving the perfect balance between DSP and control processing. CEVA-X4 has achieved great improvement over the previous generation PHY control DSP. It is the embodiment of deep baseband expertise accumulated in the industry for more than 20 years, ensuring that CEVA-X4 can be perfectly satisfied. The most demanding requirements of the 4G and 5G standards of the first generation."
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