Introduction
Successive approximation analog-to-digital converters (called SAR ADCs due to their successive approximation registers) are widely used in applications requiring up to 18-bit resolution and up to 5 MSPS. Benefits include small size, low power consumption, no pipeline delay, and ease of use.
The host processor can access or control the ADC through a variety of serial and parallel interfaces such as SPI, I2C, and LVDS. This article discusses design techniques for building reliable, complete digital interfaces, including digital power levels and sequences, I/O status during startup, interface timing, signal quality, and errors due to digital activity.
Digital I/O power level and sequence
Most SAR ADCs provide a separate digital I/O power input (VIO or VDRIVE) that determines the operating voltage and logic compatibility of the interface. This pin should have the same voltage as the host interface (MCU, DSP or FPGA) supply. The digital input should normally be between DGND-0.3 V and VIO + 0.3 V to avoid violating the absolute maximum ratings. A short decoupling capacitor must be connected between the VIO pin and DGND.
ADCs with multiple power supplies may have a clear power-up sequence. Application Note AN-932 Power Sequence provides a good reference for the design of these ADC power supplies. To avoid forward biasing the ESD diode and avoiding an unknown state when the digital core is powered up, turn on the I/O power supply before the interface circuit. Analog power supplies are typically powered up before the I/O supply, but not all ADCs. Please refer to and follow the data sheet to ensure the sequence is correct.
Digital I/O status during startup
To ensure that the initialization is correct, some SAR ADCs require certain logic states or sequences to implement digital functions such as reset, standby, or shutdown. After all power supplies have stabilized, the specified pulse or combination should be applied to ensure that the state of the ADC is as expected at startup. For example, a high pulse lasts at least 50 ns on RESET, which is a requirement for configuring the AD7606 to operate properly after power-up.
The digital pin must not be switched until all power supplies are fully established. For SAR ADCs, the conversion start pin CNVST may be sensitive to noise. In the example shown in Figure 1, the host cPLD pulls CNVST high while AVCC, DVCC, and VDRIVE are still rising. This may cause the AD7367 to go into an unknown state, so the host should keep CNVST low until the power supply is fully established.
Figure 1. Pulling CNVST high while power is rising may cause an unknown state
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